Bus structure, database and method of designing interface

ABSTRACT

With respect to each application, libraries, corresponding to operation models, for describing operations respectively attained by employing a Neumann CPU (bus structure), a Harvard CPU (bus structure) and a direction separate type CPU (bus structure) are registered. In a performance table of each library, the performance index of the library is expressed as a function of parameters of throughput, a bus width, instruction quantity and memory size. Also, a portion of the operation realized by using software and a portion realized by using hardware are registered. Through operation simulation conducted with each application successively replaced with each of the libraries, the performance of a semiconductor integrated circuit can be evaluated, so as to synthesize an optimal interface.

BACKGROUND OF THE INVENTION

The present invention relates to a bus structure in a semiconductorintegrated circuit device such as a system LSI, a method of designing aninterface and a database for use in design of an interface.

A part designated as an interface for connecting a CPU of asemiconductor circuit and a circuit controlled by the CPU isconventionally significant for communication between the CPU and thecircuit. The essential portion of the interface is a signal linedesignated as a bus, and a system for controlling data input/output, forexample, controlling how right to access to the bus is acquired, issignificant in sending data. In other words, the interface including thebus structure is an element having a great influence upon the ultimateperformance of a device.

The conventionally known bus structures are, as is shown in FIG. 1, aNeumann architecture type bus structure used in a Neumann processor anda Harvard type bus structure used in a Harvard processor. In the Neumannarchitecture type bus structure, merely an address and a data aredistinguished from each other, so that an address and a data can beexpressed together by one line or an address and a data can berespectively expressed by two lines. Known examples of the Neumannarchitecture type bus structure are a multiplexer type bus structure inwhich an address and a data are transferred through a common bus and ademultiplexer type bus structure in which an address and a data arerespectively transferred through different buses, namely, an address busand a data bus.

A Harvard processor has a structure in which data are divided dependingupon their contents into control data and data of an actuallytransferred file. A known Harvard type bus structure conventionallydeveloped is a bus structure in which the address bus is further dividedinto an IO address bus and a memory address bus and the data bus isfurther divided into a control data bus and a transfer data bus(hereinafter referred to as the data separate type bus structure).

The multiplexer type bus structure is used for serially processingcontrol and transfer of addresses and data, and the throughput attainedby this structure is comparatively low but the area occupied by the bus(bandwidth) is small. The demultiplexer type bus structure is used forprocessing control/transfer of addresses and control/transfer of data inparallel, and since the parallel processing can be conducted, higherprocessing speed is attained by this structure.

Furthermore, the data separate type bus structure, that is, theconventional Harvard type bus structure, is used for processing controland transfer in parallel with respect to both addresses and data, andhence, the throughput is further higher.

In constructing a conventional large scale device such as a system LSI,however, an appropriate method of constructing the structure of aninterface has not been established yet. Specifically, with respect tothe bus structure alone, each of the known bus structures has bothadvantages and disadvantages, and a method of integrally evaluating thebus structure in relation to the operations of respective circuits hasnot been established yet.

Moreover, the scale of semiconductor integrated circuits is increasing.Therefore, in design of, for example, a device designated as a systemLSI including a combination of plural semiconductor circuits, a flexiblyusable bus structure cannot be obtained in designing an interface byemploying any of the conventional bus structures alone.

SUMMARY OF THE INVENTION

An object of the invention is providing a design method for constructingan interface of a large scale semiconductor device such as a system LSIand a bus structure and a database for use in the design method.

The bus structure of this invention for connection between a controlcircuit and plural circuits to be controlled in a semiconductorintegrated circuit, comprises an address bus divided into an upstreambus and a downstream bus; and a data bus divided into an upstream busand a downstream bus.

According to this bus structure, restriction in concurrent instructionprocessing, for example, for transmitting a data to a given circuit tobe controlled while transmitting another data to another circuit to becontrolled, can be relaxed, resulting in improving the data processingcapability of a device using the bus structure.

In the bus structure, the data bus is preferably divided with respect toeach of the plural circuits to be controlled and each divided portion ofthe data bus is preferably further divided into an upstream bus and adownstream bus. In this manner, the restriction in concurrentinstruction processing can be further relaxed.

The database of this invention for use in design of a semiconductorintegrated circuit comprises a table including description of kinds ofbus structures for connection between a control function part and pluralapplications.

Accordingly, the database is applicable to design of an interface inwhich restriction in concurrent instruction processing, power, area andthe like varied depending upon a bus structure can be comprehensivelyconsidered.

In the database, the table preferably includes a performance tabledescribing a performance index for evaluating performance attained by anoperation model of each of the applications. In this manner, aninterface can be constructed through evaluation of the entire system.

In the database, the performance table preferably includes, as theperformance index, at least one of parameters of throughput, a buswidth, instruction quantity and memory size. In this manner, aninterface can be constructed under consideration of parameters varieddepending upon the type of bus structure.

In the database, the performance table preferably includes, as thedescription of kinds of bus structures, description of a separate typebus structure having an address bus divided into an upstream bus and adownstream bus and a data bus divided into an upstream bus and adownstream bus. In this manner, an interface can be constructed byutilizing a novel bus structure.

The first method of this invention of designing an interface forconnection between a control function part of a semiconductor integratedcircuit and plural applications by using a database storing plurallibraries corresponding to operation models of the plural applications,comprises a step of analyzing a number of collisions of bus transactionthrough an operation simulation where the applications are limitlesslyoperated by the control function part by successively using each of theplural libraries as the operation model of each of the pluralapplications.

In this method, an interface can be constructed under consideration ofcongestion caused in operating the applications and varied dependingupon selection of the libraries.

The first method of designing an interface can further comprise a stepof generating FIFOs in a number of stages according to the number ofcollisions of bus transaction, so that the number of collisions of bustransaction can be analyzed with the FIFOs virtually inserted betweenthe applications. In this manner, an interface can be designed inconsideration of performance attained by avoiding collisions of bustransaction.

The second method of this invention of designing an interface forconnection between a control function part of a semiconductor integratedcircuit and plural applications by using a database storing plurallibraries corresponding to operation models of the plural applications,comprises a step of analyzing a number of concurrent instructionprocessing through operation simulation where the applications arelimitlessly operated by the control function part by successively usingeach of the plural libraries as the operation model of each of theplural applications.

In this method, an interface can be designed considering how processingcapability of the system attained by operating the applications ischanged through selection of the libraries.

In the second method of designing an interface, a structure of a crossbar bus is preferably determined in accordance with the number ofconcurrent instruction processing. In this manner, an interface can bedesigned in consideration of performance attained by reducing the loadof the control function part and dispersing a current value.

The second method of designing an interface can further comprise a stepof generating a transfer operation control function part to be disposedin a bus where the number of concurrent instruction processing is largerthan a predetermined value, so that the number of concurrent instructionprocessing can be analyzed with the transfer operation control functionpart disposed in the bus. In this manner, an interface can be designedin consideration of performance attained when transfer operations can beconducted in parallel.

The third method of this invention of designing an interface forconnection between a control function part of a semiconductor integratedcircuit and plural applications by using a database storing plurallibraries corresponding to operation models of the plural applicationsand plural bus structures, comprises the steps of (a) setting pluralmain parameters for ultimately evaluating the semiconductor integratedcircuit and setting plural sub-parameters affecting each of the mainparameters; (b) selecting library groups where the main parameters meettarget values by evaluating each of the main parameters on the basis ofthe sub-parameters of each of the libraries; and (c) determining aninterface by selecting an optimal library group by evaluating pluralmain parameters determined with respect to each of the selected librarygroups.

In this method, as compared with a method where the performance isevaluated based on all the parameters at a time, optimal libraries canbe selected more integrally, so as to ultimately determine an optimalinterface.

The third method of designing an interface can further comprise, beforethe step (a), a step of conducting operation simulation by successivelyusing each of the plural libraries as an operation model of each of theplural applications. Thus, an optimal interface can be more accuratelydetermined. This method can be specifically carried out by any of thefollowing:

For example, in the step (a), three main parameters are set and threesub-parameters are set with respect to each of the three mainparameters; in the step (b), a three-dimensional coordinate systemhaving the three sub-parameters as coordinate axes is built forselecting a library group where an area of a triangle determinedaccording to values of the sub-parameters is smaller than a targetvalue; and in the step (c), a three-dimensional coordinate system havingthe three main parameters as coordinate axes is built for determiningthe interface based on a library group where an area of a triangledetermined according to values of the main parameters obtained from theselected library groups is minimum.

Alternatively, the method can further comprise, after the step (a) andbefore the step (b), a step of selecting a library group where aspecific sub-parameter noticed among the plural sub-parameters meets atarget value, and in the step (b), a library group where main parametersexcluding a specific parameter among the plural main parameters meettarget values is selected, and in the step (c), a library group wherethe specific main parameter is minimum is selected as the optimallibrary group.

Further alternatively, in the step (a), affecting coefficients of theplural sub-parameters affecting the main parameters are respectivelyset; in the step (b), a library group where the main parameters meettarget values is selected on the basis of the affecting coefficients andvalues of the sub-parameters; and in the step (b), plural mainparameters obtained from the selected library groups are weighted beforeselecting the library group where the main parameters meet the targetvalues.

The fourth method of this invention of designing an interface forconnection between a control function part of a semiconductor integratedcircuit and plural applications by using a database storing plurallibraries corresponding to operation models of the plural applicationsand plural bus structures, comprises the steps of (a) successivelyselecting each of the plural libraries as the operation model of each ofthe plural applications; (b) operating the plural applications by thecontrol function part, whereby analyzing performances of the controlfunction part, an interface and the applications attained by using eachof the libraries; (c) repeatedly conducting the steps (a) and (b),whereby determining an interface by selecting an optimal library groupon the basis of results of the analysis; and (d) synthesizing an optimalinterface on the basis of the determined parameters.

In this method, an optimal interface can be synthesized based onperformance evaluation of the entire system attained by operating therespective applications. Thus, a basic interface design method can beestablished.

In the fourth method of designing an interface, in the step (b), anumber of collisions of bus transaction occurring by limitlesslyoperating the applications by the control function part is preferablyanalyzed with respect to each of the libraries, and in the step (d),FIFOs in a number of stages according to the number of collisions of bustransaction are preferably inserted between the applications.

In the fourth method of designing an interface, in the step (b), anumber of concurrent instruction processing occurring by limitlesslyoperating the applications by the control function part is preferablyanalyzed with respect to each of the libraries, and in the step (d), across bar bus is preferably disposed in a bus where the number ofconcurrent instruction processing is larger than a predetermined value.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram for schematically showing structuraldifferences among conventional Neumann architecture type bus structures,a conventional Harvard type bus structure and a novel Harvard type busstructure according to Embodiment 1 of the invention;

FIGS. 2(a), 2(b) and 2(c) are diagrams for showing examples of aconventional bus structure and direction separate type bus structures(employed when a tertiary station is provided and no tertiary station isprovided) of Embodiment 1, respectively;

FIGS. 3(a), 3(b), 3(c) and 3(d) are diagrams for showing processing ofaddresses and data on time base in a Neumann multiplexer type busstructure, a Neumann demultiplexer type bus structure, a Harvard dataseparate type bus structure and the direction separate type busstructure of Embodiment 1;

FIG. 4 is a block diagram of a resource separate type bus structure ofEmbodiment 1 in which a target resource A is a memory and targetresources B and C are IOs;

FIGS. 5(a) and 5(b) are diagrams for showing examples of a library and aperformance table of unit applications A and B stored in a designdatabase according to Embodiment 2;

FIG. 6 is a block diagram for showing an example of a method ofconducting operation simulation by using plural applications inEmbodiment 2;

FIG. 7 is a diagram for showing a method of displaying transactionanalysis, that is, one performance analysis of Embodiment 2;

FIG. 8 is a diagram for showing a method of displaying instructionprocessing analysis, that is, another performance analysis of Embodiment2;

FIGS. 9(a) and 9(b) are diagrams for showing part of a bus structureresulting from providing a cross bar bus in a portion where a largenumber of concurrent instructions occur in Embodiment 2;

FIGS. 10(a), 10(b), 10(c) and 10(d) are diagrams for showing proceduresin selecting a library with a minimum cross area from libraries whoseparameters meet target values;

FIGS. 11(a), 11(b), 11(c) and 11(d) are diagrams for showing proceduresin weighting a performance index, an average power index (or a maximumpower index) and an area index, summing up the indexes to obtain a sumas an optimal index and selecting a library with a smallest optimalindex;

FIG. 12 is a block diagram for showing the structure of an optimal IFsynthesized by a method of designing an interface of Embodiment 2; and

FIG. 13 is a flowchart for showing procedures in system design includingthe synthesis of an optimal IF according to Embodiment 2.

DETAILED DESCRIPTION OF THE INVENTION Embodiment 1

FIG. 1 is a block diagram for schematically showing structuraldifferences among conventional Neumann architecture type bus structures,a conventional Harvard type bus structure and a novel Harvard type busstructure according to this embodiment.

The Harvard type bus structure of this embodiment may be designated as a“direction separate type bus structure”, which is obtained by furtherseparating transferred data to be processed in the data separate typebus structure. In the direction separate type bus structure, assumingthat target resources (circuits to be controlled) are placed around aprocessor (control circuit) at the center, the directions of sendingtransferred data are divided into an “up” direction and a “down”direction, and also the transferred data sent to the circuits to becontrolled may be divided into a memory data and an IO data. Herein, acontrol data is a data on control of, for example, recognition andresponse, and a transferred data is a batch of data such as an imagefile data.

FIG. 2(a) is a diagram of a conventional bus structure. As is shown inFIG. 2(a), merely one bus is provided between a CPU and a targetresource (i.e., a primary station IO in this drawing) in theconventional bus structure.

In contrast, in the direction separate bus type structure of thisembodiment, communication between a processor (CPU) and a primarystation is carried out separately between an upstream bus and adownstream bus as is shown in FIGS. 2(b) and 2(c). FIG. 2(b) is adiagram for showing a direction separate type bus structure employedwhen secondary and tertiary stations communicate with the CPUrespectively through primary stations, and FIG. 2(c) is a diagram forshowing a direction separate type bus structure employed when thetertiary station of FIG. 2(b) is not present.

FIGS. 3(a) through 3(d) are diagrams for showing processing of addressesand data on time base in the Neumann multiplexer type bus structure, theNeumann demultiplexer type bus structure, the Harvard data separate typebus structure and the direction separate type bus structure,respectively.

In the multiplexer type bus structure, as is shown in FIG. 3(a),addresses and data are serially processed along one line in a sense. Forexample, when a given command is to be generated for a target resourceA, a control address of the target resource A is specified, a controldata for the target resource A is sent, an address for transferring adata to the target resource A is sent, and then a transferred data issent to the target resource A. Also in generating a command for a targetresource B, similar procedures are serially carried out.

In the demultiplexer type bus structure, as is shown in FIG. 3(b),addresses and data are processed in parallel. For example, when a givencommand is to be generated for a target resource A, a control data forthe target resource A is sent while specifying a control address of thetarget resource A, and a transferred data is sent to the target resourceA while sending an address for transferring the data to the targetresource A. Also in generating a command for a target resource B,similar procedures are carried out in parallel.

In the data separate type bus structure, as is shown in FIG. 3(c), acontrol address, a transfer address, a control data and a transferreddata are processed in parallel. For example, when a given command is tobe generated for a target resource A, specification of a control addressof the target resource A, transmission of a control data to the targetresource A, transmission of an address for sending a data to the targetresource A and transmission of the transferred data to the targetresource A are carried out in parallel. Also in generating a command fora target resource B, similar procedures are carried out in parallel.

In the data separate type bus structure, as is shown in FIG. 3(d), notonly a control address, a transfer address, a control data and atransferred data are processed in parallel but also transmission of theaddresses and the data is carried out in parallel separately between theup direction and the down direction. For example, when given commandsare to be generated for target resources A, B and C, an up address or adown address is specified in specifying control addresses of the targetresources A, B and C. When the up address is specified, a transferaddress and a transferred data in the up direction (for example, for thetarget resources A and C) are sent through the upstream bus, and whenthe down address is specified, a transfer address and a transferred datain the down direction (for example, for the target resources B and A)are sent through the downstream bus. In other words, transmission oftransfer addresses and transferred data can be carried out independentlyof specification of control addresses and transmission of control data.

For example, it is assumed, in the bus structure of FIG. 2(b), that aprimary station IO 1 is a target resource A, a primary station IO 2 is atarget resource B and a secondary station is a target resource C. Inthis case, in specifying an address of the target resource A (i.e., theprimary station IO 1), the specified address of the target resource A isnot input to the target resource B (i.e., the primary station IO 2), andhence, while a transferred data is being sent to the target resource Awith the transfer address of the target resource A specified, anothertransferred data can be sent to the target resource B with a transferaddress of the target resource B specified. Furthermore, a data can beoutput (sent in the down direction) as soon as the data is input (sentin the up direction).

FIG. 4 is a block diagram for showing a resource separate type busstructure employed when a target resource A is a memory and targetresources B and C are IOs. While the CPU is receiving a data input fromthe target resource C (i.e., the IO 2) and storing the data in thetarget resource A (i.e., the memory), the CPU can send a data to thetarget resource B (i.e., the IO 1) at the same time.

Accordingly, in the conventional data separate type bus structure, timerequired for data transfer is, as is shown in FIG. 3(d), obtained byserially summing up times required for data transfer A, data transfer B,data transfer C and data transfer A (and the same can be said withrespect to time required for data transfer A, B and C and addresstransfer A). In contrast, in the direction separate type bus structureof this embodiment, time required for data transfer can be shortened asshown in FIG. 3(d). This is because, by separately providing theupstream bus and the downstream bus, the transmission of transferaddresses and transferred data in the up direction to the targetresources A and C and the transmission of transfer addresses andtransferred data in the down direction to the target resources B and Acan be simultaneously carried out.

Embodiment 2

A design method for an IF (interface) including a bus structureaccording to Embodiment 2 of the invention will now be described.Procedures for designing an optimal IF are as follows:

—Data to be Prepared—

First, data necessary for performance analysis (library models) will bedescribed. It is necessary to create an operation model with respect toeach unit application. As an exemplified method of creating an operationmodel, an operation model is basically created by using software, and itis determined, with respect to each operation model, what percentagesare created by using hardware. A unit application is defined by theinput/output relationship of one application and is not defined in therange. Examples of the unit application are a transfer operation ofprint data by using IrDA, transfer of the positional data of a mouse byusing a USB, and compression and decompression of still image data byusing JPEG. In using an application for data transfer using infraredcommunication designated as “IrDA”, data for printing should bepreviously processed on a computer side. For example, the data iscompressed by JPEG for compressing a still image, the format isconverted for expressing the data as infrared, and then the data istransferred by the infrared communication. In this case, a unitapplication herein corresponds to processing prescribed by the input andthe output of the application designated as IrDA excluding theprocessing prior to the infrared communication (IrDA).

The processing time is varied depending upon whether an operation modelis created by using hardware or software. In this embodiment, it isdetermined which part of an operation model is created by using hardwareor software on the basis of a portion where respective layers aredivided more or less definitely in expression of one protocol.

FIGS. 5(a) and 5(b) are diagrams for showing examples of a library and aperformance table of unit applications A and B stored in a designdatabase. When it is assumed, for example, that there are libraries Aand B at specification level for the applications A and B, respectively,performance tables corresponding to operation models describingoperations attained by employing, as the CPU (bus structure), theNeumann architecture type CPU (bus structure), the conventional Harvardtype CPU (bus structure) and the direction separate type CPU (busstructure) are registered with respect to each of the applications A andB as shown in FIGS. 5(a) and 5(b). In each performance table of eachlibrary, the performance index of the library is expressed as a functionof parameters of throughput (P), a bus width (B), instruction quantity(M) and memory size (E).

In FIGS. 5(a) and 5(b), hatched portions in the description of theoperations of the libraries are realized by using software and portionswithout hatching are realized by using hardware. When it is assumed, inthe application A, that the performance index is 100 when all thefunctions are realized by using software, the performance index is, forexample, 50 if 40% of the functions are realized by using hardware andremaining 60% of the functions are realized by using software, and theperformance index is 10 if 60% of the functions are realized by usinghardware. The performance tables are thus prepared so as to show theperformance indexes attained by replacing what percentage of softwarewith hardware.

In the functions of the operation model, “FLOW” corresponds to a layerfor describing a flow of procedures, such as, for example, whenprocesses a and b are to be conducted, “the process a is followed by theprocess b”. Also, “MANG” corresponds to a layer for describing a methodof managing communication between applications, such as, for example,when different file transfer applications are connected to each other,multiplexers of data exchange necessary for the applications.Furthermore, “LINK” corresponds to a layer for defining procedures inlinkage, for example, for allowing one information data to be recognizedas a data surrounded by a series of data such as a sync bit, a controldata, a MAC data and an ending. Moreover, “PHY” corresponds to a layerfor defining an actual coding method, for example, when “1” is to beexpressed, for determining whether or not “1” is expressed at a givenpulse width or at the center of a given pulse width. Also, “CAL”corresponds to a layer for indicating, for example, in arithmeticprocessing, whether the calculation processing (such as multiplication)is carried out by using hardware or software.

Furthermore, it is necessary to take it consideration that whenprocessing is carried out by using software, high performance isrequired but the performance may be lower by utilizing hardware to someextent. Although the performance tables as shown in FIGS. 5(a) and 5(b)are prepared with respect to a large number of applications, FIGS. 5(a)and 5(b) merely exemplify the applications A and B.

—Operation Simulation—

FIG. 6 is a block diagram for showing an example of a method ofconducting operation simulation by using plural applications. Herein, itis assumed that a library realized by using software by 100% is used foran application A, that a library realized by using hardware by 20% isused for an application B and that a library realized by using hardwareby 40% is used for an application C, so as to analyze the performance intransfer processing of these three applications.

At this point, in the connection shown in FIG. 6, a portion for countinginputs and outputs (input/output count part) and a portion for countinginstruction processing (instruction count part) are described in theoperation analysis simulation. For example, when the applications A, Band C are connected to a transfer processing ile (system operationcontrol), the input/output count part counts the number of collisions ofinput/output between the processor and respective circuits (collisionsof bus transaction) occurring if the transfer processing is carried outwithout any management. In other words, the input/output count partmeasures the congestion of buses. Also, it counts the number ofinstruction processing including the collisions.

FIG. 7 is a diagram for showing a method of displaying transactionanalysis in this performance analysis. As is shown in FIG. 7, withrespect to each of the applications A, B and C and with respect to eachof the cases of employing the library of the Neumann architecture typebus structure (demultiplexer type), the library of the conventionalHarvard type bus structure (data separate type) and the library of thedirection separate type bus structure, the transaction densities betweenthe applications A and B, the applications B and C and the applicationsA and C measured by the input/output count part are arranged onprocessing time base. In FIG. 7, a higher hatching density indicates alarger number of collisions. In employing the Neumann architecture typebus structure, the number of collisions is unavoidably large whenparallel processing is carried out. In contrast, in employing thedirection separate type bus structure, the number of collisions iscomparatively small because parallel processing can be easily carriedout in this structure. Then, a FIFO is inserted into a portion where alarge number of collisions occur. For example, in employing the Neumannarchitecture type bus structure, k stages (for example, ten stages) ofFIFOs are inserted between the applications A and B, l stages (forexample, eight stages) of FIFOs are inserted between the applications Band C, and l stages of FIFOs are inserted between the applications A andC. Alternatively, in employing the conventional Harvard (data separatetype) bus structure, l stages of FIFOs are inserted between theapplications A and B, m stages (for example, six stages) of FIFOs areinserted between the applications B and C, and m stages of FIFOs areinserted between the applications A and C. Furthermore, in employing thedirection separate type bus structure, n stages (for example, fourstages) of FIFOs are inserted between the applications A and B, n stagesof FIFOs are inserted between the applications B and C and n stages ofFIFOs are inserted between the applications A and C. It is necessary tostore information in FIFOs during the processing of the CPU, and thenumber of stages of FIFOs to be inserted is analyzed in accordance withthe congestion of the bus. It goes without saying that the number ofstages of FIFOs to be inserted is smaller as the number of collisions ofthe bus transaction is smaller. In this manner, in accordance with eachbus structure, namely, the structure of each bus connected to the CPU,the number of stages of FIFOs to be inserted is determined.

FIG. 8 is a diagram for showing a method of displaying the instructionprocessing analysis in this performance analysis. As is shown in FIG. 8,with respect to each of the applications A, B and C and with respect toeach of the cases of employing the library of the Neumann (demultiplexertype) bus structure, the library of the conventional Harvard (dataseparate type) bus structure and the library of the direction separatetype bus structure, concurrent instruction densities between theapplications A and B, the applications B and C and the applications Aand C measured by the instruction count part are arranged on processingtime base. In FIG. 8, a higher hatching density indicates a largernumber of concurrent instructions, namely, higher throughput of theentire system. In employing the Neumann architecture type bus structure,the number of concurrent instructions is small. In contrast, inemploying the direction separate type bus structure, the number ofconcurrent instructions is comparatively large. When the number ofconcurrent instructions is larger, the processing time is shorter andthe response speed is higher, but on the contrary, there arises aproblem that the load of the CPU is larger and an instant current valueis larger.

FIGS. 9(a) and 9(b) are diagrams for showing part of a bus structure inwhich a cross bar bus is provided in a portion here a large number ofconcurrent instructions occur. As is shown in FIG. 9(a), when the CPUhas a reserve in its function, a portion not generally used is providedwith a transfer function of the application B and the CPU controlsswitching of the cross bar bus. Alternatively, as is shown in FIG. 9(b),when the CPU does not have a reserve or the like, a DMA is provided. TheDMA (direct memory access) has a transfer function to allow direct datatransfer between an input/output controller and a main storage notthrough the CPU. In other words, the CPU does not control all theprocessing but a cross bar bus having a switching function is providedand the function of the DMA is utilized, and the cross bar bus isswitched so that, for example, the application A can be processed by theCPU and the application B can be processed by the DMA. In this manner,the load of the CPU can be reduced and a current value can be dispersed.This newly added element may be a CPU instead of the DMA as far as ithas a transfer function. In this case, attention should be paid to aportion where the largest number of concurrent instructions occur, so asto determine whether no cross bar bus is provided, a single cross barbus is provided or a double cross bar bus is provided on the basis ofthe maximum number of concurrent instructions occurring in employing agiven type of CPU.

—Analysis Index—

Next, a method of selecting the optimal performance among theperformances obtained as a result of the aforementioned analyses will bedescribed. The most significant parameters for evaluating a system areherein designated as main parameters, and it is herein assumed that themain parameters are performance, power and area. In consideration ofthree sub-parameters affecting each of these main parameters as a whole,a library group with the main parameters respectively falling withintarget ranges is first selected. Then, on the basis of the values of themain parameters of the selected library group, an optimal library groupis comprehensively selected.

The optimal library group is specifically selected by any of thefollowing methods:

1. Method for Selecting Libraries with Minimum Cross Area:

FIGS. 10(a) through 10(d) are diagrams for showing procedures in amethod for selecting a library with a minimum cross area among librarieshaving satisfactory parameters.

First, as is shown in FIG. 10(a), the number of collisions of bustransaction, the processing quantity and the response time are set asthe three sub-parameters affecting the main parameter, “performance”,and a three-dimensional coordinate system having these sub-parameters asthe coordinate axes is built. The values of the three sub-parameters areobtained on the basis of the analysis resulting from the operationsimulation conducted by using the libraries corresponding to theoperation models of the respective applications. The values are uniquelydefined depending upon, for example, whether the Neumann architecturetype bus structure, the conventional Harvard type bus structure or thedirection separate type bus structure is employed for each of the unitapplications A, B and C connected to the CPU, and what percentages ofthe operation of each application is realized by using hardware. Forexample, on the basis of the analysis results shown in FIGS. 7 and 8,the number of collisions of bus transaction and the processing time areobtained. At this point, the worst value or the average value of thenumber of collisions of transaction between respective IOs, the averagevalue in the entire system or the average value in a given section canbe determined as transaction T. The execution (simulation) time requiredin conducting the data analysis as shown in FIGS. 7 and 8 is determinedas response time R. The execution processing quantity (sum) required inconducting the analysis of FIGS. 7 and 8 is determined as processingquantity E.

The performance of a system LSI is higher as the bus transaction T issmaller, the processing quantity E is smaller and the response time R isshorter. Therefore, the main parameter, performance, is better as thecross area in the three-dimensional coordinate system is smaller.Accordingly, a library group in which a cross area between thecoordinate axes of the coordinate system and a plane formed by linkingrespective values (values of the sub-parameters) on the coordinate axesis smaller than a given target value is selected. This cross area may berelatively regarded as the value of “performance”.

Also, as is shown in FIG. 10(b), the processing quantity E, a hardwareratio H and a concurrent active density A are determined as the threesub-parameters affecting the main parameter, “power”, and athree-dimensional coordinate system having the three sub-parameters asthe coordinate axes is built. The hardware ratio H corresponds to thepercentages of hardware in each operation model shown in FIG. 6. Theconcurrent active density A corresponds to the ratio of concurrentlyactivated buses obtained in the analyses of FIGS. 7 and 8. In this case,the power can be smaller as the processing quantity E is smaller, thehardware ratio H is smaller and the concurrent active density A issmaller. Therefore, the main parameter of power is better as the crossarea in the three-dimensional coordinate system is smaller. Accordingly,a library group in which a cross area between the coordinate axes of thecoordinate system and a plane formed by linking respective points(values of the sub-parameters) on the coordinate axes is smaller than agiven target value is selected. This cross area may be relativelyregarded as the value of “power”. In this case, evaluation can be madebased on either the peak value of power or the average value of power.

Furthermore, as is shown in FIG. 10(c), a necessary bus width B,necessary memory size M and the FIFO quantity F of FIFOs to be insertedare determined as the three sub-parameters affecting the main parameter,“area (cost)”, and a three-dimensional coordinate system having thesub-parameters as the coordinate axes is built. The bus width Bcorresponds to the total width of buses in the bus structure of eachoperation model of FIG. 6. The memory size M corresponds to memory sizeused in each operation model of FIG. 6. The FIFO quantity F correspondsto the sum of stages of FIFOs determined as a result of the analyses ofFIGS. 7 and 8. In this case, the main parameter of area is better as thebus width B is smaller, the memory size M is smaller and the FIFOquantity F is smaller. Accordingly, a library group in which a crossarea between the coordinate axes of the coordinate system and a planeformed by linking respective points (values of the sub-parameters) onthe coordinate axes is smaller than a given target value is selected.This cross area may be relatively regarded as the value of “area”.

Then, as is shown in FIG. 10(d), a three-dimensional coordinate systemhaving the main parameters, namely, performance, power and area, as thecoordinate axes is built. Thereafter, a library group in which a crossarea (area of a triangle) between the coordinate axes and a plane formedby linking values of the main parameters determined based on the librarygroups selected through the procedures of FIGS. 3(a) through 3(c),namely, the values of performance, power and area (the cross areas ofFIGS. 10(a) through 10(c), is minimum is selected. Then, an interfacedetermined based on the selected library group is determined as theoptimal interface.

2. Method for Selecting Libraries with Laying Stress on SpecificParameters:

For example, on the basis of the analysis results shown in FIGS. 7 and8, a library with a sub-parameter of bus transaction smaller than apredetermined value is selected among libraries having satisfactoryresponse time as another sub-parameter, a library with a sub-parameterof processing quantity smaller than a predetermined value is selectedamong libraries having satisfactory response time as anothersub-parameter, a library with a sub-parameter of bus width smaller thana predetermined value is selected among libraries having satisfactorymemory size as another sub-parameter, and a library with a sub-parameterof bus width smaller than a predetermined value is selected amonglibraries having satisfactory FIFO quantity as another sub-parameter.

Then, among the libraries selected as described above, optimal librariesare comprehensively selected on the basis of the following points. Theoptimal libraries are variously selected depending upon the kind or thelike of a circuit device to be designed as follows:

First, from the selected libraries, libraries whose main parameters ofperformance and power meet target minimum performance and target maximumpower are selected. Then, among the thus selected libraries, a librarygroup whose main parameter of area is smallest is selected as theoptimal library group.

Secondly, from the selected libraries, libraries whose main parametersof performance and power meet target minimum performance and targetmaximum power are selected. Then, among the thus selected libraries, alibrary group whose main parameter of average power is smallest isselected as the optimal library group.

Thirdly, from the selected libraries, libraries whose main parameters ofarea and maximum power meet target maximum area and target maximum powerare selected. Then, among the thus selected libraries, a library groupwhose main parameter of performance is smallest is selected as theoptimal library group.

Fourthly, from the selected libraries, libraries whose main parameter ofarea and maximum power meet target maximum area and target maximum powerare selected. Then, among the thus selected libraries, a library groupwhose main parameter of average power is smallest is selected as theoptimal library group.

3. Method for Selecting Libraries by Using Weighted Indexes:

In this method, as is shown in FIGS. 11(a) through 11(d), a performanceindex x of the main parameter of performance, an average power index yav(or a maximum power index ymx) of the main parameter of power and anarea index z of the main parameter of area are respectively weighted bya, b and c, and the resultants are summed up to obtain a total value asan optimal index. Then, a library having a smallest optimal index isselected.

In this case, the performance index x is calculated as follows: As isshown in FIG. 11(a), the response time R and its performance affectingcoefficient l_(x), the bus transaction T and its performance affectingcoefficient m_(x), and the processing quantity E and its performanceaffecting coefficient n_(x) are respectively calculated. Then, theperformance index x is calculated by the following formula:Performance index x=Rl _(x) ×Tm _(x) ×En _(x)The performance affecting coefficient l_(x) of the response time is “1”when the response time is, for example, 1 second. In other words, whenthe response time is 3 seconds, the performance affecting coefficientl_(x) of the response time is “3”. The performance affecting coefficientm_(x) of the bus transaction is “1” when 10 collisions occur. In otherwords, when 20 collisions occur, the performance affecting coefficientm_(x) of the bus transaction is “2”. The performance affectingcoefficient n_(x) of the processing quantity is “1” when the processingquantity is 10 MIPS (wherein 1 MIPS corresponds to millioninstructions). In other words, when the processing quantity is 50 MIPS,the performance affecting coefficient n_(x) of the processing quantityis “5”.

The power index y is calculated as follows: As is shown in FIG. 11(b),average processing quantity Eav (or maximum processing quantity Emx) andits power affecting coefficient l_(y), the hardware ratio H and itspower affecting coefficient m_(y), and average concurrent active ratioAav (or a maximum concurrent active ratio Amx) and its power affectingcoefficient n_(y) are respectively calculated. Then, the power index yis calculated by the following formula:Power index y=Eavl _(y) ×Hm _(y) ×Aavn _(y) or =Emxl_(y) ×Hm _(y) ×Amxn_(y)The power affecting coefficient l_(y) of the average processing quantity(or the maximum processing quantity) is “1” when the processing quantityis, for example, 10 MIPS. The power affecting coefficient m_(y) of thehardware ratio is “1” when the hardware ratio is 20%. In other words,when the hardware ratio is 40%, the power affecting coefficient m_(y) ofthe hardware ratio is “2”. The power affecting coefficient n_(y) of theaverage concurrent active ratio (or the maximum concurrent active ratio)is “1” when the concurrent active ratio is 25%. In other words, when theconcurrent active ratio is 10%, the power affecting coefficient n_(y) ofthe average concurrent active ratio is “0.5”.

The area index z is calculated as follows: As is shown in FIG. 11(b),the memory size M and its area affecting coefficient l_(x), the FIFOquantity F and its area affecting coefficient m_(x), and the bus width Band its area affecting coefficient n_(x), are respectively calculated.Then, the area index z is calculated by the following formula:Area index z=Ml _(z) ×Fm _(z) ×Bn _(z)The area affecting coefficient l_(x) of the memory size is “1” when thememory size is, for example, 1 kByte. In other words, when the memorysize is 10 kBytes, the area affecting coefficient l_(z) of the memorysize is “10”. The area affecting coefficient m_(x) of the FIFO quantityis “1” when the FIFO quantity is 128 bytes. In other words, when theFIFO quantity is 256 bytes, the area affecting coefficient m_(x), of theFIFO quantity is “2”. The area affecting coefficient n_(z) of the buswidth is “1” when the bus width is 16 bits. In other words, when the buswidth is 8 bits, the area affecting coefficient n_(z) of the bus widthis “0.5”.

Then, as is shown in FIG. 11(d), with respect to the performance indexx, the power index y and the area index z calculated as described above,affecting coefficients (weighting coefficients) a, b and c arerespectively determined, and the resultants are summed up to obtain anoptimal index. Specifically, the optimal index Op is calculated by thefollowing formula:Optimal index Op=ax+by+czThen, a library having a smallest optical index Op is ultimatelyselected.

—Synthesis of Optimal IF—

FIG. 12 is a block diagram for showing the structure of an optimal IFsynthesized through the aforementioned procedures. In a bus structureselected based on the aforementioned analysis indexes, FIFOs areinserted into necessary portions, so as to construct a bus structurecapable of concurrent processing. In FIG. 12, a portion surrounded witha dotted-and-dashed line excluding the DMA corresponds to the IF(interface). Specifically, the bus structure including a data bus, acontrol bus, a cross bar bus and the like and the inserted FIFOstogether form the IF for connecting hardware of the libraries A, B andC, the CPU (operation model) and a storage device (such as a RAM and aROM).

FIG. 13 is a flowchart for showing procedures in system design includingthe synthesis of an optimal IF described in this embodiment.

First, libraries A, B and C similar to those shown in FIGS. 5(a) and5(b), and the Harvard type bus structure, the Neumann (demultiplexertype) bus structure, the direction separate type bus structure and thelike are stored as the database.

Then, a bus structure is selected for a selected library in step ST1,and a system connection diagram, a transfer processing file, a newlibrary and the like are input in step ST2.

Next, in step ST3, transaction and instruction processing are analyzed.At this point, the transaction analysis shown in FIG. 7 and theinstruction processing analysis shown in FIG. 8 are carried out throughthe operation simulation shown in FIG. 6, so as to determine the numberof stages of FIFOs to be inserted and to provide a necessary cross barbus.

Then, in step ST4, the analysis index is determined by, for example, anyof the aforementioned three methods (shown in FIGS. 10(a) through 10(d)and 11(a) through 11(d). By repeating the procedures of steps ST1through ST4, a system having a smallest optimal index Op is selected. Insteps ST3 and ST4, performance evaluation of both hardware and software(HW/SW performance evaluation) is conducted.

Next, in steps ST5 through ST7, the optimal system is divided betweenhardware and software. Specifically, an optimal IF is synthesized instep ST5, and a system connection diagram as shown in FIG. 12 isgenerated in step ST6. On the other hand, in step ST7, software(conditions) such as an application, flow control and OS (operationsystem) is selected.

Ultimately, in step ST8, coordination between hardware and software isverified. Specifically, it is verified whether or not software cansatisfactorily function by using hardware.

In the design method for an interface of this embodiment, operationsimulation is conducted by using a library corresponding an operationmodel registered with respect to each bus structure and eachapplication. On the basis of sub-parameters and main parameters obtainedas a result of the operation simulation, the performance of the entiresystem connected through the interface can be accurately evaluated in anenvironment close to actual use. Then, on the basis of the evaluation,an interface most suitable to requirement of a designer can be selected,so as to construct the entire system.

1. A bus structure for connection between a control circuit and pluralcircuits to be controlled in a semiconductor integrated circuit,comprising: an address bus divided into an upstream bus and a downstreambus; and a data bus divided into an upstream bus and a downstream bus.2. The bus structure of claim 1, wherein said data bus is divided withrespect to each of said plural circuits to be controlled and eachdivided portion of said data bus is further divided into an upstream busand a downstream bus.
 3. A database for use in design of a semiconductorintegrated circuit comprising: a table including description of kinds ofbus structures for connection between a control function part and pluralapplications.
 4. The database of claim 3, wherein said table includes aperformance table describing a performance index for evaluatingperformance attained by an operation model of each of said applications.5. The database of claim 4, wherein said performance table includes, assaid performance index, at least one of parameters of throughput, a buswidth, instruction quantity and memory size.
 6. The database of claim 3,wherein said performance table includes, as the description of kinds ofbus structures, description of a separate type bus structure having anaddress bus divided into an upstream bus and a downstream bus and a databus divided into an upstream bus and a downstream bus. 7-19. (canceled)